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An improved fast mode decision algorithm for VLSI architecture implementation

J. CHARLES RAJESH KUMAR1,* , T. VANCHINATHAN2, P. SUDHARSAN2

Affiliation

  1. Lecturer, Department of Electrical & Computer Engineering, Effat University, Kingdom of Saudi Arabia
  2. Director – AXIIP Semiconductor (P) Ltd

Abstract

For better video quality in the H.264/AVC video coding technology, motion estimation has massive growth due to improvements in searching algorithms and improved significantly in compression efficiency and complexity, specifically in area, power and throughput. In this paper, an efficient sum of absolute difference (SAD) tree and its hardware architecture have proposed in Residue Number System (RNS) based moduli and implements the full search variable block size motion estimation (FSVBSME). The main advantage is that for performing carry free addition operation, residue number system is being considered as a non weighted number system to binary number system, RNS is mostly suitable for image compression techniques and loss of image quality is very less. In hardware implementation, it occupies less area and takes less execution time for output result. This proposed architecture is capable of achieving the less hardware cost and logical elements, high throughput required to perform real time motion estimation. Experimental results show that synthesized with TSMC 180nm CMOS, the proposed design occupies 12.9k logic gates at 352MHZ and consumes 19mW power to encode 1920X1088 HDTV video frames at 30 frames per second..

Keywords

SAD RNS adder, SAD comparator, Mode decision.

Citation

J. CHARLES RAJESH KUMAR, T. VANCHINATHAN, P. SUDHARSAN, An improved fast mode decision algorithm for VLSI architecture implementation, Optoelectronics and Advanced Materials - Rapid Communications, 9, 5-6, May-June 2015, pp.738-745 (2015).

Submitted at: April 9, 2015

Accepted at: May 7, 2015