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Design and FPGA implementation of reconfigurable OFDM with improved PAPR

N. MANIKANDA DEVARAJAN1,* , M. CHANDRASEKARAN2

Affiliation

  1. Associate Professor, Department of Electronics and Communication Engineering, VMKV Engineering College, Salem, India
  2. Professor & Head, Department of Electronics and Communication Engineering, GCE, Bargur, India

Abstract

The Orthogonal Frequency Division Multiplexing (OFDM) is used in various modern day wireless standards. It can be realized in two ways namely, Fast Fourier Transform (FFT) and Discrete Wavelet Transform (DWT). The OFDM-FFT shows a performance improvement in terms of area, speed and power but fails to improve Peak-to-Average-Power-Ratio (PAPR). On the other hand the OFDM-DWT shows a promising improvement in terms of PAPR. This paper presents a reconfigurable Orthogonal Frequency Division Multiplexing (OFDM), which will configure between the Fast Fourier Transform (FFT) and Discrete Wavelet Transform (DWT) based on the application needs. The proposed reconfigurable OFDM is developed using Verilog HDL and targeted in Xilinx Virtex 5 FPGA (xc5v1x30ff324). The proposed OFDM shows a remarkable performance improvement in terms of Peak-to-Average-Power-Ratio (PAPR) at the cost of area overhead. The area overhead is due to the Discrete Wavelet Transform (DWT) architecture which consumes 16.14% more Gate Element (GE) than the Fast Fourier Transform (FFT) architecture. However, the proposed architecture with shared resources saves 58.67% and 57.05% sliced LUT and Gate Element (GE) respectively..

Keywords

OFDM, FFT, DWT, Reconfigurable OFDM, PAPR, FPGA implementation.

Citation

N. MANIKANDA DEVARAJAN, M. CHANDRASEKARAN, Design and FPGA implementation of reconfigurable OFDM with improved PAPR, Optoelectronics and Advanced Materials - Rapid Communications, 9, 5-6, May-June 2015, pp.561-566 (2015).

Submitted at: April 7, 2015

Accepted at: May 7, 2015