Abstract
A novel technique for FPGA implementation of potentially jamming-resistant and high-resolution synthetic aperture radar
(SAR) system using UWB-OFDM architecture has been presented. The greater computation time and larger memory
requirement is still the main difficulties in processing huge SAR raw data in real-time UWB SAR imaging. Significant part of
the computation time is related to compression of raw data in range and cross-range domain which in turns heavily depends
on computing FFT, IFFT and complex multiplication as part of SAR imaging. A shared memory based FPGA model is
developed using Xilinx block-set which is able to perform range and azimuth compression with high accuracy. The design
procedures are straightforward and can be applied to any practical SAR system for real-time imaging. The model is
designed as hardware co-simulation using Xilinx system generator and implemented on Xilinx Virtex-6 ML605 FPGA..
Keywords
Field Programmable Gate Araay (FPGA), Ultra-wideband (UWB), Orthogonal frequency division multiplexing (OFDM),
Synthetic Aperture Radar (SAR).
Citation
MD ANOWAR HOSSAIN, IBRAHIM ELSHAFIEY, MAJEED A. S. ALKANHAL, Shared memory based real-time implementation of UWB-OFDM SAR imaging system, Optoelectronics and Advanced Materials - Rapid Communications, 8, 7-8, July-August 2014, pp.635-642 (2014).
Submitted at: May 19, 2014
Accepted at: July 10, 2014